The article explains why 128-byte alignment is often preferred over the standard 64-byte cache line size for preventing false sharing on modern x64 processors. It highlights that Intel's spatial prefetcher loads cache lines in pairs from Sandy Bridge onwards, making 128-byte spacing more effective at avoiding cache line contention. Benchmarks on AWS c5d and c6i instances support this optimization strategy.
Background
False sharing occurs when multiple threads modify different variables located on the same cache line, causing unnecessary cache coherence traffic. This article provides a deep dive into CPU microarchitecture specifics to optimize multi-threaded performance.
- Source
- Lobsters
- Published
- Jul 7, 2026 at 04:22 PM
- Score
- 6.0 / 10