The article examines how LLVM emits conditional branches when compiling branch-free C code for 32-bit RISC-V, using 128-bit integer addition as a case study. It explains that unlike x86 and AArch64, RISC-V lacks instructions like conditional moves, forcing the compiler to use branches for carry propagation. The analysis also touches on constant-time coding patterns and bit masking techniques relevant to the discussion.
Background
RISC-V is an open-source instruction set architecture that has been gaining traction but sometimes lacks certain instructions available on more mature architectures like x86 and ARM. LLVM is the compiler infrastructure that targets multiple architectures including RISC-V.
- Source
- Lobsters
- Published
- Oct 10, 2026 at 03:31 AM
- Score
- 6.0 / 10