The article presents a technique for converting integer division and modulo operations into floating-point arithmetic, leveraging the fact that FP division often has lower latency and higher throughput on current hardware. The author shows that for integers fitting within 53/24 bits (double/single precision), truncation and FMA operations can replicate integer divide and remainder. This approach avoids expensive rounding-mode switches and can be applied in performance-critical code paths.
Background
Integer division on modern CPUs typically suffers from high latency (20-80+ cycles) and low throughput compared to floating-point division, making this a relevant optimization topic for performance-sensitive code. The technique is particularly useful in scenarios where divisors are known at compile time or in tight numerical loops.
- Source
- Lobsters
- Published
- Aug 11, 2026 at 04:17 AM
- Score
- 5.0 / 10