A developer explores cache coherence issues on a Terasic DE0-Nano-SOC board featuring dual ARM Cortex-A9 cores. The blog post walks through hardware setup, the MMU, memory types, and the underlying problem of why the two cores lack proper cache coherence.
Background
The Terasic DE0-Nano-SOC is an Altera Cyclone-V SoC devkit combining ARM Cortex-A9 processors with an FPGA fabric. Cache coherence between multiple ARM cores is a well-known challenge in embedded SoC design, particularly when software-configured MMU settings don't enable coherent protocols.
- Source
- Lobsters
- Published
- Aug 23, 2026 at 12:48 PM
- Score
- 5.0 / 10